// ------------------------------------------------------------------
// File_name: AndOr.sv
// Describe : Combinational logic using & and |.
// ------------------------------------------------------------------
// Author   : QilinZhao
// Version  : v-1.0
// Date     : 2013-06-28
// E-mail   : forqilin@163.com
// copyright: QiXin Studio
// ------------------------------------------------------------------

// module header may includes:
// moudle name, port direction, port width and port types

// and , or, not, xor : primitives
module AndOr (
  output X, Y, 
  input  A, B, C
);

  assign #10 X = A & B;
  assign #10 Y = B | C;
endmodule
